It is an inexorable fact of life that all electronic assemblies – from the most complex, densely interconnected systems to the cheapest mass-produced consumer devices – will eventually fail. Such devices may be victims of various forms of abuse at the hands of their end users, subject to mechanical, environmental, or electrical stresses far beyond what any design engineer would consider reasonable. Some, especially early prototypes, may be inherently flawed and susceptible to malfunction as a result of a simple mistake made during one too many late night, bleary-eyed design review sessions, conducted over energy drinks and cold takeout. Of course, it is also possible for assemblies to simply die of old age; eventually, normal wear and tear will break down even the most robust of electronic devices. In all these cases, the result is the same (at least at a very high level): a device that no longer performs its intended function.
The process of dissecting the remains of a failed device or assembly, slicing through the tangled web of interconnects and dielectrics to get to the kernel of truth lying at the root cause of the malfunction, is called failure analysis. By utilizing an extensive set of specialized tools and techniques, failure analysts can go from a very basic initial observation (e.g. “no output on J8 pin-4”) to actionable data (“via misalignment between layer 1 and 3 on the trace from U9 pin-6 to J8 pin-4”). Traversing the gap between these two points requires a meticulously detailed approach. In future columns, we will delve into the intricacies of this approach by reviewing individual case studies and techniques, to better show how failure analysis can be applied within an existing manufacturing environment to improve product reliability; in this column, we will provide a high-level overview of what the failure analysis process looks like.
Due to the nature of failure analysis, no two projects will ever be quite the same. Failure modes, environmental conditions, device applications – all these parameters shape the circumstances of a given failure analysis project. Despite the fact that all failures are unique, there is still a generic process that can be applied to drive an investigation to its resolution. This process starts with the verification of the problem as reported – whether that report comes from a consumer, an entity further down the supply chain, or even from a test engineer directly after production, it is vital to verify that the issue can be recreated before attempting any further analysis. The verification phase of a project may be as simple as a five minute check with a multimeter, proving that the correct voltage is not outputting on a given pin or that continuity does not appear between two nodes that should be connected; in other cases, a more complicated approach may be necessary, such as when a failure is only present when a device is operated within a certain temperature range. Verifying the failure is not important only to prove that a problem exists; the verification phase also allows the failure analyst to determine the proper test conditions for later steps of the process.
Verification of the failure is the first of many steps in non-destructive testing (or NDT) of a device. As the name implies, non-destructive tests should have minimal impact on the sample under analysis; ideally, these tests should carry little to no risk of damaging the sample or potentially losing the defect. These tests will generally include a detailed visual inspection, looking for macro-scale defects like cracked solder joints or broken traces. X-ray inspection may reveal things that are buried within a circuit board or hidden underneath a component, like via misregistration or improperly wetted BGA balls. An acoustic microscope may reveal component level failures, such as package delamination inside a component that was not properly stored before undergoing reflow. Generally speaking, non-destructive tests are not sufficient to prove the root cause of failure on their own; however, they provide key data that will shape the course of the failure analysis project.