Wafer Test & Sort

Probe Testing

Wafer-level probe testing applies a programmed test pattern to each die on the wafer to collect data about the electrical circuit. Spirit offers a vast array of electrical tests to meet application-specific data needs depending on the wafer complexity. Our process is cost-effective based on die size, number of touch downs and performance o maximize the rate of return and optimize test coverage to the data sheet.

Sort & Bin

Wafer probe testing determines the reliability and performance limits of each die on the wafer. This data allows you to sort die into performance ranges, optimizing each die’s performance in application. This is especially useful for die stacking and multi-chip designs. Binning reduces low-lot yields, production cost and rework.

Three Temp Test

Electrical testing at three temperatures covers additional test parameters for quality and integrity of the die in harsh-environment or mission-critical applications.

Wafer Test Capabilities

  • Wafer Speed Binning
  • Wafer Temperature Binning
  • Wafer “in family” data segregation
  • Known Good Die
  • Waffle/Gel Pack sorting
  • Function Tests
  • AC parameters
  • DC parameters
  • Application specific I/O test
  • Customer configured testing
  • Data sheet verification
  • Anti-counterfeit validation

Failure Protection

Products testing outside of specifications or standards pose a failure risk. Improperly leaded finishes can result in whiskering over time.

If your product fails analysis, you can take immediate action to refinish leads, or in the case of failed connection mapping, disqualify an entire lot. Ask us about our testing warranty protection to prevent failures from impacting cost and production time.